The present invention relates, in general, to the field of integrated circuit ("IC") devices. More particularly, the present invention relates to integrated circuit devices, for example, asynchronous and synchronous dynamic random access memory ("DRAM") devices, for which a fast data access is needed in conjunction with a pipelined data architecture.
Current integrated circuit devices tend to incorporate an excessive number of gate delays in their output data paths through the inclusion of a number of multiplexers deemed necessary to achieve acceptable levels of multiplexing. Moreover, such devices also tend to include extremely complicated anticipatory clock circuits implemented as phase locked loops ("PLLs"), delay locked loops ("DLLs"), time delay mirrors ("TDMs") and the like which must be implemented in order to achieve the overall desired device speed. Since most current integrated circuit devices do not provide for a minimum clock cycle, the on-chip area required to support such anticipatory clock circuits is prohibitively large. Still other devices attempt to speed up the output data path by "over-driving" the associated circuit nodes which is also done at the expense of device power and on-chip area constraints.